While the present invention is not limited to field effect transistors, and may find application in bipolar, CMOS, or other semiconductor technology, reference will be made to field effect transistors, often referred to as NOS transistors. Fundamentally, NOS transistors generally comprise highly doped regions in a semiconductor region with a gate region or channel between the highly doped regions. The highly doped regions are often called source and drain regions. A gate electrode is located above the channel and is sometimes called the "gate". Often, NOS transistors are separated electrically from nearby transistors or other devices by some isolation technique. One prevalent technique involves the use of a relatively thick field oxide. Another technique is a field shield approach. The field shield approach is disclosed, for example, in U.S. Pat. No. 4,570,331, entitled "Thick Oxide Field-Shield CMOS Process, issued on Feb. 18, 1986 to INMOS Corporation upon the application of S. Sheffield Eaton, Jr. and Cheng-Cheng Hu.
In addition to isolating the transistor, for there to be utility, connections must be made to the "electrodes" of the transistor, specifically to the two source/drain regions and the gate electrode.
Metal silicides are known to be effective in making low resistance contacts to source/drain electrodes of N+ doped silicon and for making low resistance bit line interconnects in DRAMs. However, boron from P+ silicon readily migrates from the silicon to the metal silicides to form metal borides. Excessive migration of boron from the sources and drains of p-channel transistors causes CMOS integrated circuits to fail. One object of the present invention, therefore, is to provide against the migration of dopant material in integrated circuit structures.
Second, it is recognized in the semiconductor art that moderately doped regions are useful to join heavily doped source and drain regions of MOS transistors to the channel region which underlies the gate electrode. Extra complexity has been introduced into process flows to allow the formation of such moderately doped regions. It is therefore a further object of the present invention to provide a simple solution to this problem.
Third, MOS transistors used in integrated circuits generally include a relatively thick interlevel dielectric which is added on top of the transistor structure. After the dielectric is in place, at some subsequent time, windows are etched to open the contacts to the transistor source, drain and gate electrodes. Etch processes used to open these contacts tend to damage these electrode regions of the transistor. In consequence, a third main object of the present invention is to provide a structure and process which protects elements of the transistor from such damage due to etching.
It will be understood that the preferred form of the invention involves the use of a titanium nitride (TiN) layer covering a titanium silicide (TiSi.sub.2) region that is found in the contact area. This part of the combination is known to the semiconductor industry, and reference may be had to Stevens (one of the present co-inventors), McClure and Hill, U.S. Pat. No. 4,784,973 issued on Nov. 15, 1988 to INMOS Corporation, entitled "Semiconductor Contact Silicide/Nitride Process with Control for Silicide Thickness." That patent explains also that titanium nitride can be used as a metallurgic barrier against reactions between a silicon substrate and an aluminum contact material to a source or drain, for example. The '973 patent discloses a process using a control layer located in the contact opening and formed illustratively of a compound of silicon, oxygen and nitrogen, or silicon oxide. A layer of titanium is added, titanium silicide is formed under the control layer, and titanium nitride is formed above the control layer. It may also be noted, however, that the titanium is added after a relatively thick layer of dielectric such as BPSG (boro-phosphosilicate glass) is established.
By way of further background, an application of the combination of titanium nitride with titanium silicide is discussed by Tang et al. in "VLSI Local Interconnect Level Using Titanium Nitride," International Electron Devices Meeting 1985 (IEDM 85), pp. 590-93. Tang et al. use the titanium nitride for local interconnects.
The present invention has further aspects, however, than merely combining a titanium nitride layer with a titanium silicide region in the contact area. These further aspects are discussed infra.
One of the further objectives of integrated circuit (IC) manufacturing is to increase the functional capability of the IC chip while maintaining the smallest overall chip area and while maintaining process simplicity. Interconnect technology has been a major area of focus in scaling down the overall chip layout. As chip contact size and interconnect design rules are scaled down, new interconnect technologies are needed to maintain reasonable device design features such as contact resistance and interconnect sheet resistance. Furthermore, as design rules shrink, the need for planarized features on the chip is even more important. Thus, new interconnect technologies are needed which are capable of scaling, but which also provide improved contact and interconnect device characteristics, planarization features, and overall cost effective manufacture ability.
The use of metal silicides for application as an interconnect material has been previously disclosed. For example, the use of titanium silicide in a self aligned "salicide" process has been described by Alperin et al. in IEEE Trans. on Electron Devices, vol. ED-32, p. 141. Further, using a TiN/TiSi.sub.2 clad layer for source and drain moat region salicide formation and using TiN as a local interconnect layer has been described by Holloway et al. in U.S. Pat. Nos. 4,657,628 and 4,746,219, Tang et al. in U.S. Pat. Nos. 4,676,866 and 4,690,730, and by Havemann et al. in U.S. Pat. No. 4,788,160. These patents also specifically describe: the elimination of buried contacts in SRAM design, control of N+ and P+ dopant migration through the local interconnect layer, a diffusion barrier to aluminum metalization, and a field area overlap and contact etch stop feature. The subject matter of the present invention, while including all of the advantages cited by Holloway et al., Tang et al., and Havemann et al., is a further enhancement of the art.
The salicide structures shown in Holloway et al., Tang et al., and Havemann et al. have a TiSi.sub.2 layer as a primary conductive layer shunting the polysilicon gate or other doped source, drain, or moat areas. TiN (which is electrically conductive) is used primarily as a local interconnect to strap silicided circuit features. The structures depicted in the drawings in these patents rely heavily on both TiSi.sub.2 and TiN as conductive layers. The dependence on TiSi.sub.2 as a primary conductive layer in this structure imposes severe limitations on its use in conjunction with a subsequent high temperature reflow process.
Holloway et al., Tang et al., and Havemann et al. all disclose similar means for the formation of the TiSi.sub.2 or TiN/TiSi.sub.2 clad layer, i.e. sputter depositing a 600 .ANG. to 2000 .ANG. titanium layer, annealing at 500.degree. C. to 750.degree. C. in nitrogen for up to 90 minutes, photo patterning, and etching by a dry/wet etch process to remove unwanted TiN. Variations on this procedure include depositing an oxide hard mask layer such as TEOS oxide over the deposited Ti, patterning the hard mask layer, and then annealing in nitrogen and argon to react the titanium to form the TiSi.sub.2 /TiN clad layer. All of these procedures produce a TiSi.sub.2 layer which is generally greater than 1000 .ANG. in thickness.
The thickness of the TiSi.sub.2 layer is critical because of two possible adverse problems which can occur during a high temperature anneal: dopant segregation and agglomeration. A high temperature anneal at temperatures from 850.degree. C. to 920.degree. C., commonly referred to as a reflow process, is widely used in the industry to flow a BPSG or PSG doped oxide film and provide planarization over the underlying topography.
Dopant segregation at the TiSi.sub.2 to P+ or N+ interface can cause severe contact resistance problems. Results reported by Scott et al. in IEEE Trans. on Electron Devices, vol. ED-34, p. 562 conclude that the post silicide processing temperature must be kept at or below 700.degree. C. to avoid contact resistance problems with TiSi.sub.2 to boron P+ junctions and TiSi.sub.2 to phosphorus N+ junctions. Scott et al. conclude that 900.degree. C. post silicide processing is compatible with only arsenic doped N+ junctions and is completely incompatible with boron doped junctions. Scott et al. discloses depositing a 1000 .ANG. Ti film over P+ and N+ junction areas and annealing to form TiSi.sub.2 layers (thicknesses were not reported).
In a study by Y. Taur et al., IEEE Trans. On Electron Devices, vol. ED-34, p. 575, however, contact resistivities of 3.times.10.sup.-7 and 1.times.10.sup.-6 .OMEGA..cm.sup.2 were obtained for TiSi.sub.2 to N+ and TiSi.sub.2 to P+ contacts respectively if the interface dopant density was maintained at 1.times.10.sup.20 /cm.sup.3. Taur et al. disclose that reasonable contact resistance can be obtained following a 900.degree. C. post silicidation anneal if a minimal amount of the silicon junction is consumed during TiSi.sub.2 formation. Taur et al. uses a 350 .ANG. to 500 .ANG. titanium film deposited over P+ and N+ junction areas and annealed to form TiSi.sub.2 layers (TiSi.sub.2 &lt;800 .ANG. thickness).
Agglomeration of the TiSi.sub.2 layer during a high temperature anneal is another problem. Agglomeration can cause a large increase in silicided source/drain sheet resistance or polycide sheet resistance and can lead to excessive junction leakage or gate oxide degradation. Thicker TiSi.sub.2 layers appear to be more resistant to sheet resistance increases caused by TiSi.sub.2 agglomeration. But thicker TiSi.sub.2 is also more likely to cause junction leakage problems unless the underlying P+ and N+ junctions are deep (approximately 2.times. the TiSi.sub.2 thickness). Thicker TiSi.sub.2 is also more likely to degrade gate oxide in silicided poly gate structures unless the underlying polysilicon is thick. Thus, scaling limitations may exist in the devices described in Holloway et al., Tang et al., and Havemann et al. as a result of TiSi.sub.2 induced junction leakage or gate oxide degradation.
The devices and processes described in Holloway et al., Tang et al., and Havemann et al. are severely limited in their manufacturing application due to dopant redistribution and oxidation during high temperature reflow. Where TiSi.sub.2 is used as a primary conductive layer, a relatively thick (&gt;1000 .ANG.) TiSi.sub.2 layer must be used in order to maintain low sheet resistance. There is no other provision made for application in a high temperature reflow environment except avoiding the use of TiSi.sub.2 to P+ contacts at high temperature (900.degree. C.) or restricting use of the application to low temperature (700.degree. C.). Further, use is restricted to a nonoxidizing ambient (nitrogen or argon) during a subsequent anneal. This is less desirable than the preferred practice in the industry of using an oxidizing ambient to enhance the reflow and desification of overlying BPSG or PSG glass layers. Furthermore, in the case of a low temperature application, expensive or unusual means must be used to achieve planarization, such as deposition and etchback planarization, or a low temperature high pressure anneal in nitrogen as described by Chapman et al. in IEDM Technical Digest 1991, p. 101. Therefore, it is a general object of the present invention to provide an improved structure and process which overcomes these limitations in the art.
Previously, Stevens in U.S. Pat. No. 4,977,440 disclosed a TiSi.sub.2 /TiN structure to provide low contact resistance, a metallurgical barrier, interconnect regions, and improved mechanical strength to wire bonding. Although Stevens uses TiSi.sub.2 /TiN over contact areas, the structure also includes aluminum over TiN regions. Since aluminum is not a refractory material, Stevens' structure should not be used in a high temperature reflow application. Thus, Steven' structure is not appropriate for use in a buried local interconnect application.
Butler, U.S. Pat. No. 5,043,790 discloses a contact structure wherein a conductive nitride layer is located within the contact region and a first dielectric is located partially inside and partially outside of the contact region. A sidewall of another dielectric is located outside of the conductive nitride layer so that a conductive material can be located within the contact region to be electrically coupled to one electrode but not another, even when the conductive material extends outside the contact region and over the electrode to which contact is not to be made. This is accomplished through widening the contact region using a dry etch followed by a wet etch. Butler, U.S. Pat. No. 5,216,281 discloses another embodiment of this structure.
The present invention is an improvement over the structure of Butler and the other cited references.